1. Field of the Invention
The present invention relates to power on reset circuits, and more specifically, to a power on reset circuit generating a power on reset signal for a prescribed period of time after power supply is turned on.
2. Description of the Background Art
In most semiconductor integrated circuit devices including DRAMs (Dynamic Random Access Memories), SRAMs (Static Random Access Memories) and microprocessors, a power on reset circuit is employed. The power on reset circuit generates a power on reset signal for a prescribed period of time after power supply is turned on so as to initiate an internal circuit which has been in an unstable state before power supply is turned on. The power on reset signal is activated for a prescribed period of time until power supply voltage attains a prescribed level, after which it is inactivated. The above mentioned internal circuit is reset in response to the activated power on reset signal.
Recently, a semiconductor integrated circuit device which employs two different power supply voltages is also available. In addition, the semiconductor integrated circuit device may be tested by increasing or dropping power supply voltage. Here, higher and lower power supply voltages are respectively defined as high and low power supply voltages. Some DRAMs, for example, employ high power supply voltage of 5.0V in normal operation mode and low power supply voltage of 1.3V in standby operation mode.
When such a semiconductor integrated circuit device is employed in the conventional power on reset circuit, the internal circuit fails to be reset when power supply voltage is returned from low to high power supply voltage. More specifically, the conventional power on reset circuit fails to generate the power on reset signal unless power supply voltage increases again after dropping below 0.76V. In a DRAM where low power supply voltage of 1.3V is employed during standby operation mode, for example, the internal circuit is not reset unless the power on reset signal is generated after the end of standby operation mode.